Research library
Chips and computing hardware: completion history
All area pages | Area definition | Scoring rubric
Created November 7, 2026. The three earlier snapshots are retrospective judgment-based estimates, not scores recorded at the time. The current assessment is unchanged. Historical confidence is very low; current confidence is low. Zero can indicate an evidence gap rather than absent capability.
Chart layout updated November 8, 2026: one graph with four dated lines. Scores and assessment dates are unchanged. Overlapping lines indicate equal values; point labels show November 7, 2026. The table below contains every date's exact values.
Scalable graph | Combined 14-page report
Percentage estimates
| Measurable outcome | Nov 7, 2025 (reconstructed) | May 7, 2026 (reconstructed) | Oct 7, 2026 (reconstructed) | Nov 7, 2026 (saved) |
|---|---|---|---|---|
| Design productivity | 45% | 45% | 45% | 45% |
| Development feedback | 35% | 35% | 35% | 35% |
| Generalization | 35% | 35% | 35% | 35% |
| Manufacturability | 30% | 30% | 30% | 30% |
| Power, performance, and area | 30% | 30% | 30% | 30% |
| Useful AI efficiency | 35% | 35% | 40% | 40% |
Reconstruction notes and component scores
Components below are execution / breadth / agenda-setting / validation / sustained autonomous improvement, each out of 20. Their sum gives the percentage. The component values are judgments, not published statistics. Source links document evidence available by the cutoff, not the numerical estimate itself. The source section lists availability dates and version caveats. No area-wide average is calculated.
Design productivity
The documented floorplanning capability predates all cutoffs; full signoff labor remains unmeasured, so no later gain is assigned.
| Assessment date | Component points | Evidence used |
|---|---|---|
| 2025-11-07 (reconstructed) | 15 / 10 / 5 / 10 / 5 = 45% | chip |
| 2026-05-07 (reconstructed) | 15 / 10 / 5 / 10 / 5 = 45% | chip |
| 2026-10-07 (reconstructed) | 15 / 10 / 5 / 10 / 5 = 45% | chip |
| 2026-11-07 (saved) | 15 / 10 / 5 / 10 / 5 = 45% | Original score and evidence |
Development feedback
Circuit optimization was public by May 2025. The downstream causal research gain remains unknown throughout.
| Assessment date | Component points | Evidence used |
|---|---|---|
| 2025-11-07 (reconstructed) | 10 / 5 / 5 / 10 / 5 = 35% | evolve25 |
| 2026-05-07 (reconstructed) | 10 / 5 / 5 / 10 / 5 = 35% | evolve25 |
| 2026-10-07 (reconstructed) | 10 / 5 / 5 / 10 / 5 = 35% | evolve25 |
| 2026-11-07 (saved) | 10 / 5 / 5 / 10 / 5 = 35% | Original score and evidence |
Generalization
Multiple TPU generations support bounded transfer at every date; no new unseen-block denominator supports a changed estimate.
| Assessment date | Component points | Evidence used |
|---|---|---|
| 2025-11-07 (reconstructed) | 10 / 10 / 5 / 5 / 5 = 35% | chip |
| 2026-05-07 (reconstructed) | 10 / 10 / 5 / 5 / 5 = 35% | chip |
| 2026-10-07 (reconstructed) | 10 / 10 / 5 / 5 / 5 = 35% | chip |
| 2026-11-07 (saved) | 10 / 10 / 5 / 5 / 5 = 35% | Original score and evidence |
Manufacturability
Production use was already established, while matched yield and respin evidence is absent throughout.
| Assessment date | Component points | Evidence used |
|---|---|---|
| 2025-11-07 (reconstructed) | 10 / 5 / 5 / 5 / 5 = 30% | chip |
| 2026-05-07 (reconstructed) | 10 / 5 / 5 / 5 / 5 = 30% | chip |
| 2026-10-07 (reconstructed) | 10 / 5 / 5 / 5 / 5 = 30% | chip |
| 2026-11-07 (saved) | 10 / 5 / 5 / 5 / 5 = 30% | Original score and evidence |
Power, performance, and area
Useful layouts predate every snapshot. A joint matched-node PPA comparison is still missing, so the estimate stays flat.
| Assessment date | Component points | Evidence used |
|---|---|---|
| 2025-11-07 (reconstructed) | 10 / 5 / 5 / 5 / 5 = 30% | chip |
| 2026-05-07 (reconstructed) | 10 / 5 / 5 / 5 / 5 = 30% | chip |
| 2026-10-07 (reconstructed) | 10 / 5 / 5 / 5 / 5 = 30% | chip |
| 2026-11-07 (saved) | 10 / 5 / 5 / 5 / 5 = 30% | Original score and evidence |
Useful AI efficiency
The older inference suite supports reproducible efficiency assessment. The September 2026 multi-round evidence adds limited breadth credit, not proof of AI-designed-chip gains.
| Assessment date | Component points | Evidence used |
|---|---|---|
| 2025-11-07 (reconstructed) | 10 / 5 / 5 / 10 / 5 = 35% | mlperf25 |
| 2026-05-07 (reconstructed) | 10 / 5 / 5 / 10 / 5 = 35% | mlperf25 |
| 2026-10-07 (reconstructed) | 10 / 10 / 5 / 10 / 5 = 40% | mlperf |
| 2026-11-07 (saved) | 10 / 10 / 5 / 10 / 5 = 40% | Original score and evidence |
Dated sources
All sources accessed November 7, 2026. Dates below are publication or conservative availability dates, as noted.
chip | 2024-09-26 - Google DeepMind: AlphaChip. Floorplanning and TPU use; full design and manufacturing autonomy not established.
evolve25 | 2025-05-14 - AlphaEvolve announcement. Evaluated code optimization and narrow feedback into AI training; human-defined evaluators.
mlperf25 | 2025-09-09 - MLPerf Inference v5.1. Standardized system throughput testing; not proof of AI designing the improvements.
mlperf | 2026-09-17 - MLCommons: MLPerf Inference v6.1. Inference throughput trends; not autonomous chip-development attribution.
Future updates
Keep these reconstructions separate from subsequently recorded observations. Append new dated assessments with changed component scores and source evidence; do not silently replace historical reasoning. The shared historical-method notes describe how these snapshots were made.