Research library
Chips and computing hardware
View the four-date completion graphs and reconstruction notes.
Promise and evidence
Better chip design could make AI and scientific computing cheaper and more energy efficient. AlphaChip's developer report describes reinforcement learning for chip layout and its use in TPU design. Layout optimization is one part of hardware development, not an autonomous replacement for the complete design and manufacturing process.
Apply the shared measurement protocol. Targets are proposed.
Dated baseline coverage
All linked measurable-outcome files below contain an evidence baseline reviewed November 7, 2026, with source dates, findings, limitations and follow-up measurements. These distinguish measured results from proxies and unknown values; they do not assert that proposed milestones are achieved. See the baseline coverage notes.
Progress estimates
Judgment-based estimates as of November 7, 2026, using the same 0–100% scale and five-part rubric as mathematics. 0% anchors the period before ChatGPT's public release in 2022; 100% requires AI to manage this field's continuing advancement without human participation. Confidence is low. These are evidence-based judgments, not empirical completion measurements, forecasts or percentages of jobs replaced.
| Measurable outcome | Estimated progress | Execution / breadth / agenda / validation / improvement (each out of 20) |
|---|---|---|
| Design productivity | 45% | 15 / 10 / 5 / 10 / 5 |
| Development feedback | 35% | 10 / 5 / 5 / 10 / 5 |
| Generalization | 35% | 10 / 10 / 5 / 5 / 5 |
| Manufacturability | 30% | 10 / 5 / 5 / 5 / 5 |
| Power performance and area | 30% | 10 / 5 / 5 / 5 / 5 |
| Useful ai efficiency | 40% | 10 / 10 / 5 / 10 / 5 |
Each linked outcome explains its score, cites its dated evidence baseline and identifies the next measurement. Zero indicates no qualifying post-anchor progress established by the reviewed evidence for that outcome, not proof of no relevant capability. Do not average these overlapping indicators into a field-wide percentage or interpret their differences as a precise ranking of fields. All outcomes reaching 100% would still require a separate field-wide demonstration of sustained autonomous advancement.
Measurable features
| Feature | Measurement and acceptance rule |
|---|---|
| Design productivity | Engineer hours and calendar days from frozen specification to signoff, including verification, repair, and fabrication preparation. |
| Power, performance, and area | Watts, achieved clock or workload throughput, and square millimeters at the same process node, operating conditions, and constraints. Report tradeoffs, not only the best dimension. |
| Useful AI efficiency | Joules and total dollars per training run reaching fixed quality, or per inference meeting fixed accuracy and latency. Include memory and communication overhead. |
| Manufacturability | Design-rule violations, silicon yield, timing failures, and number of fabrication revisions. |
| Generalization | Fraction of unfamiliar chip blocks meeting all constraints without task-specific manual tuning. |
| Development feedback | Verified reduction in resources or time for subsequent AI research caused by the hardware improvement. |
Evidence requirements
Separate simulation, physical-design signoff, and fabricated-silicon measurements. Compare against a strong contemporary electronic-design-automation workflow with equal tuning budgets. Document the process node, foundry libraries, area limits, thermal limits, workload, and host system. Do not attribute a process-node advance or larger chip solely to AI design.
Proposed milestones
On ten held-out blocks, reduce total design labor by at least 25% while meeting every signoff constraint and remaining within preregistered power, performance, and area margins.
Fabricate at least one design and independently confirm at least 10% better energy per matched workload without an unacceptable yield or reliability loss.
Replicate the gain across two chip families and report total manufacturing and deployment costs.
Demonstrate that the resulting hardware accelerates a subsequent AI research cycle at equal quality, net of hardware-development costs. This connects hardware progress to AI feedback.