Design productivity

Area: definition. Apply the shared measurement protocol.

Estimated progress toward AI-managed chips

45% complete — judgment-based estimate as of November 7, 2026. Confidence: low. The scale starts at 0% before ChatGPT's public release in 2022 and ends at 100% when AI manages the field's continuing advancement without human participation. This rates the outcome's contribution to that transition, not the percentage of tasks solved, a measured fraction of the field, or time remaining.

The shared scoring rubric uses five equally weighted dimensions: execution, breadth, agenda-setting, validation, and sustained autonomous improvement. Points for this outcome are 15 + 10 + 5 + 10 + 5 = 45/100, in that order; each dimension has a maximum of 20. These component judgments make the estimate inspectable, but are not independently measured scores.

Reason for the estimate: Fast floorplanning across chip designs demonstrates a mature subtask. Full specification-to-signoff work, verification and repair still require substantial human involvement. The dated baseline below supplies the findings and source links used for this assessment. Unmeasured components receive no demonstrated-progress credit; missing evidence does not prove a missing capability.

What would move the score: Time complete comparable blocks from frozen specification to signoff, counting verification, manual edits and fabrication preparation. Higher autonomy scores additionally require AI to select worthwhile work, validate results and improve the process over repeated cycles without human research management, repair or adjudication. Lower the score if replication fails, quality regresses or previously hidden human assistance is found. Preserve this dated estimate when adding future assessments.

Measurement and acceptance rule

Engineer hours and calendar days from frozen specification to signoff, including verification, repair, and fabrication preparation.

Evidence requirements

Separate simulation, physical-design signoff, and fabricated-silicon measurements. Compare against a strong contemporary electronic-design-automation workflow with equal tuning budgets. Document the process node, foundry libraries, area limits, thermal limits, workload, and host system. Do not attribute a process-node advance or larger chip solely to AI design.

Related milestones

See the area's proposed milestones. Proposed targets are distinct from the dated evidence below.

Baseline as of November 7 2026

Status: Demonstrated subtask speed; full signoff metric unknown. Sources accessed November 7, 2026. This is a documentary baseline, not an independent replication or an assertion of the worldwide best result. An unknown measurement is not zero.

Dated findings

September 26, 2024: Google reports AlphaChip producing chip floorplans in hours rather than weeks or months of human effort. Google DeepMind: AlphaChip.

Interpretation and tracking value

Floorplanning is only one design stage. Full specification-to-signoff engineer hours, verification and repair are not quantified by this comparison.

Next comparable measurement

Time complete comparable blocks from frozen specification to signoff, counting verification, manual edits and fabrication preparation. Preserve this dated observation; append future results with their model/system version, denominator, budget and evidence level rather than overwriting it.