Manufacturability

Area: definition. Apply the shared measurement protocol.

Estimated progress toward AI-managed chips

30% complete — judgment-based estimate as of November 7, 2026. Confidence: low. The scale starts at 0% before ChatGPT's public release in 2022 and ends at 100% when AI manages the field's continuing advancement without human participation. This rates the outcome's contribution to that transition, not the percentage of tasks solved, a measured fraction of the field, or time remaining.

The shared scoring rubric uses five equally weighted dimensions: execution, breadth, agenda-setting, validation, and sustained autonomous improvement. Points for this outcome are 10 + 5 + 5 + 5 + 5 = 30/100, in that order; each dimension has a maximum of 20. These component judgments make the estimate inspectable, but are not independently measured scores.

Reason for the estimate: Production deployment demonstrates feasibility. Yield, timing failures and respins are not reported as a matched autonomous-design comparison. The dated baseline below supplies the findings and source links used for this assessment. Unmeasured components receive no demonstrated-progress credit; missing evidence does not prove a missing capability.

What would move the score: Compare fabricated matched blocks at the same node; publish yield, design-rule violations, timing escapes and respins. Higher autonomy scores additionally require AI to select worthwhile work, validate results and improve the process over repeated cycles without human research management, repair or adjudication. Lower the score if replication fails, quality regresses or previously hidden human assistance is found. Preserve this dated estimate when adding future assessments.

Measurement and acceptance rule

Design-rule violations, silicon yield, timing failures, and number of fabrication revisions.

Evidence requirements

Separate simulation, physical-design signoff, and fabricated-silicon measurements. Compare against a strong contemporary electronic-design-automation workflow with equal tuning budgets. Document the process node, foundry libraries, area limits, thermal limits, workload, and host system. Do not attribute a process-node advance or larger chip solely to AI design.

Related milestones

See the area's proposed milestones. Proposed targets are distinct from the dated evidence below.

Baseline as of November 7 2026

Status: Production use; yield comparison unknown. Sources accessed November 7, 2026. This is a documentary baseline, not an independent replication or an assertion of the worldwide best result. An unknown measurement is not zero.

Dated findings

September 26, 2024: AlphaChip layouts have been used in successive Google TPU generations since 2020. Google DeepMind: AlphaChip.

Interpretation and tracking value

Production use establishes practical feasibility but does not disclose matched silicon yield, timing-failure rates or fabrication revisions.

Next comparable measurement

Compare fabricated matched blocks at the same node; publish yield, design-rule violations, timing escapes and respins. Preserve this dated observation; append future results with their model/system version, denominator, budget and evidence level rather than overwriting it.