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Computing hardware

Can AI design better chips and reduce the power, time and money needed to run them?

36%

field summary estimate

6 outcomes · Assessed November 7, 2026 · Low confidence

The field estimate averages its outcome scores. It is a reading aid, not a measured fraction of the field that AI manages.

How the estimate built up.

Each band is one outcome's share of the field estimate, so the top line is the estimate itself. Every field starts at 0% on December 31, 2022. Dates before the latest are retrospective estimates. Point at a band to see that outcome's score on each date.

Useful AI efficiency40%
Power, performance, and area30%
Manufacturability30%
Generalization35%
Development feedback35%
Design productivity45%

View exact historical values and reconstruction notes

What we measure

Each percentage is a judgment about progress toward independent advancement. Open the evidence to inspect the basis for it.

Design productivity

45%estimated progress

What we track

Engineer hours and calendar days from frozen specification to signoff, including verification, repair, and fabrication preparation.

Why this estimate?

Fast floorplanning across chip designs demonstrates a mature subtask. Full specification-to-signoff work, verification and repair still require substantial human involvement.

Advancements

Synopsys DSO.ai reaches first 100 commercial tape-outsFebruary 7, 2023. Synopsys reported that customers had completed the first 100 commercial tape-outs using its DSO.ai reinforcement-learning design tool, with customer results of more than 3x productivity increases; STMicroelectronics reported more than 3x higher PPA-exploration productivity on the first commercial tape-out using AI on the cloud.
NVIDIA ChipNeMo: domain-adapted LLMs for chip design tasksOctober 31, 2023. NVIDIA researchers adapted LLMs to chip design and evaluated them on an engineering assistant chatbot, EDA script generation, and bug summarization and analysis; the largest model, ChipNeMo-70B, outperformed GPT-4 on the chatbot and EDA script generation and was competitive on bug summarization.
AlphaChip produces chip floorplans in hoursSeptember 26, 2024. Google reports AlphaChip producing chip floorplans in hours rather than weeks or months of human effort.
Princeton deep-learning inverse design synthesizes mm-wave chip structures in minutesDecember 30, 2024. A Nature Communications paper from Princeton and IIT Madras reported deep-learning inverse design of multi-port radio-frequency and sub-terahertz structures co-designed with circuits; Princeton states the method synthesizes complex structures in minutes where conventional algorithms may take weeks, and that humans must still correct faulty outputs.
Design Conductor agent builds a RISC-V CPU from spec to GDSII in 12 hours6 February 2026. Verkor's Design Conductor agent autonomously produced a complete RISC-V CPU (VerCore, rv32i-zmmul) from a 219-word requirements document in 12 hours; the layout meets timing at 1.48 GHz on the ASAP7 PDK and scores 3261 on CoreMark. The output is tape-out-ready GDSII, not fabricated silicon.
Cadence launches ChipStack AI Super Agent for design and verificationFebruary 10, 2026. Cadence released an agentic AI tool for front-end chip design and verification, claiming up to 10X productivity improvements; Altera reported verification effort reduced by approximately 10X in some areas, and Tenstorrent reported up to 4X faster formal verification in a three-month evaluation on three design blocks.

Read the dated findings and sources

Status: Demonstrated subtask speed; full signoff metric unknown. Sources accessed November 7, 2026. This is a documentary baseline, not an independent replication or an assertion of the worldwide best result. An unknown measurement is not zero.

Dated findings

September 26, 2024: Google reports AlphaChip producing chip floorplans in hours rather than weeks or months of human effort. Google DeepMind: AlphaChip.

Interpretation and tracking value

Floorplanning is only one design stage. Full specification-to-signoff engineer hours, verification and repair are not quantified by this comparison.

Next comparable measurement

Time complete comparable blocks from frozen specification to signoff, counting verification, manual edits and fabrication preparation. Preserve this dated observation; append future results with their model/system version, denominator, budget and evidence level rather than overwriting it.

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Development feedback

35%estimated progress

What we track

Verified reduction in resources or time for subsequent AI research caused by the hardware improvement.

Why this estimate?

Function-preserving circuit optimization shows a plausible feedback mechanism, but the downstream effect on AI research has not been causally measured.

Advancements

MLPerf Training v5.1: Llama 3.1 405B trained in 10 minutes on BlackwellNovember 12, 2025. NVIDIA reported a 10-minute time-to-train on the Llama 3.1 405B pretraining benchmark using more than 5,000 Blackwell GPUs, 2.7x faster than the best Blackwell result of the prior round; at the same GPU count, Blackwell Ultra GB300 delivered over 4x the Llama 3.1 405B pretraining performance of the Hopper generation.
AlphaEvolve simplifies a hardware circuitDecember 9, 2025. AlphaEvolve simplified a hardware circuit while retaining its function.

Read the dated findings and sources

Status: Demonstrated design optimization; downstream causal gain unknown. Sources accessed November 7, 2026. This is a documentary baseline, not an independent replication or an assertion of the worldwide best result. An unknown measurement is not zero.

Dated findings

December 9, 2025: AlphaEvolve simplified a hardware circuit while retaining its function. Google Cloud: AlphaEvolve results.

Interpretation and tracking value

Circuit-level success is not a measured reduction in the time or resources of subsequent AI research; software-kernel speedups must not be attributed to this hardware change.

Next comparable measurement

Benchmark fabricated hardware on fixed training workloads and isolate the circuit change's effect on research throughput and quality. Preserve this dated observation; append future results with their model/system version, denominator, budget and evidence level rather than overwriting it.

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Generalization

35%estimated progress

What we track

Fraction of unfamiliar chip blocks meeting all constraints without task-specific manual tuning.

Why this estimate?

Use across TPU generations supports transfer beyond one layout; the unseen-block pass fraction without manual tuning is still unknown.

Advancements

Updated assessment questions AlphaChip-style RL macro placement21 February 2023. Cheng et al. evaluated Google's Circuit Training RL macro placer against a stronger simulated-annealing baseline and other macro placers on new sub-10nm public benchmarks, using post-route power, performance and area from a commercial tool, and identified whether its scalability and pre-training methodology have been confirmed as open questions.
ChiPFormer transfers a placement policy to unseen circuits26 June 2023. ChiPFormer, an offline decision-transformer placement method, supports fine-tuning on unseen chip circuits that reduces placement runtime from hours to minutes; evaluated on 32 chip circuits, it reported better placement quality with a 10x runtime reduction versus recent state-of-the-art approaches.
Diffusion model places unseen circuits zero-shot17 July 2024. A diffusion model trained on synthetic data placed new, realistic circuits zero-shot, without the per-circuit online training used by reinforcement-learning placers, and reported competitive performance on placement benchmarks compared with state-of-the-art methods.
AlphaChip is applied across successive TPU designsSeptember 26, 2024. AlphaChip was applied across successive TPU designs.

Read the dated findings and sources

Status: Deployment transfer; held-out pass fraction unknown. Sources accessed November 7, 2026. This is a documentary baseline, not an independent replication or an assertion of the worldwide best result. An unknown measurement is not zero.

Dated findings

September 26, 2024: AlphaChip was applied across successive TPU designs. Google DeepMind: AlphaChip.

Interpretation and tracking value

This does not establish the fraction of unfamiliar blocks meeting every constraint without block-specific tuning; task selection and training exposure matter.

Next comparable measurement

Freeze previously unseen blocks and constraints; record all attempts, retraining, manual tuning and complete signoff success. Preserve this dated observation; append future results with their model/system version, denominator, budget and evidence level rather than overwriting it.

Open the full research note

Manufacturability

30%estimated progress

What we track

Design-rule violations, silicon yield, timing failures, and number of fabrication revisions.

Why this estimate?

Production deployment demonstrates feasibility. Yield, timing failures and respins are not reported as a matched autonomous-design comparison.

Advancements

Chip-Chat: LLM-written 8-bit processor sent to tapeout on Skywater 130nm22 May 2023. Researchers co-designed an 8-bit accumulator-based microprocessor with a conversational LLM and sent it to tapeout on a Skywater 130nm shuttle, which the authors believe is the first wholly AI-written HDL for tapeout.
Automatically designed RISC-V CPU taped out and runs LinuxJune 21, 2023. Researchers generated an industrial-scale RISC-V CPU within 5 hours from input-output observations alone; the taped-out CPU runs Linux and performs comparably to the human-designed Intel 80486SX.
AlphaChip layouts ship in Google TPUs since 2020September 26, 2024. AlphaChip layouts have been used in successive Google TPU generations since 2020.

Read the dated findings and sources

Status: Production use; yield comparison unknown. Sources accessed November 7, 2026. This is a documentary baseline, not an independent replication or an assertion of the worldwide best result. An unknown measurement is not zero.

Dated findings

September 26, 2024: AlphaChip layouts have been used in successive Google TPU generations since 2020. Google DeepMind: AlphaChip.

Interpretation and tracking value

Production use establishes practical feasibility but does not disclose matched silicon yield, timing-failure rates or fabrication revisions.

Next comparable measurement

Compare fabricated matched blocks at the same node; publish yield, design-rule violations, timing escapes and respins. Preserve this dated observation; append future results with their model/system version, denominator, budget and evidence level rather than overwriting it.

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Power, performance, and area

30%estimated progress

What we track

Watts, achieved clock or workload throughput, and square millimeters at the same process node, operating conditions, and constraints. Report tradeoffs, not only the best dimension.

Why this estimate?

Useful deployed layouts merit bounded execution credit, but a complete matched-node power/performance/area comparison and autonomous tradeoff management are missing.

Advancements

NVIDIA PrefixRL circuits are up to 25% smaller at the same delayJuly 8, 2022. NVIDIA reported that reinforcement-learning-designed arithmetic circuits were up to 25% smaller in area than those from a state-of-the-art EDA tool at the same delay (64-bit adders), and that nearly 13,000 instances of AI-designed circuits are in its Hopper GPU architecture.
SK hynix reports 15% cell area reduction and 5% die shrink with DSO.aiFebruary 7, 2023. In Synopsys's 100-tape-out announcement, SK hynix reported that DSO.ai delivered a 15% cell area reduction and a 5% die shrink in a recent project; Synopsys also cited customer results of up to 25% lower total power.
NVIDIA CircuitVAE finds smaller, faster adders with half the sample budgetJune 13, 2024. CircuitVAE, which optimizes circuits in a learned continuous latent space, typically found smaller and faster 64-bit adders than reinforcement learning and genetic algorithms using less than half the sample budget, and designed adders in a real-world chip that outperformed commercial tools.
AlphaChip improves layouts for deployed TPU designsSeptember 26, 2024. Google describes improved layouts for deployed TPU designs using AlphaChip.

Read the dated findings and sources

Status: Reported design benefit; matched PPA baseline incomplete. Sources accessed November 7, 2026. This is a documentary baseline, not an independent replication or an assertion of the worldwide best result. An unknown measurement is not zero.

Dated findings

September 26, 2024: Google describes improved layouts for deployed TPU designs using AlphaChip. Google DeepMind: AlphaChip.

Interpretation and tracking value

The public narrative is insufficient to assign a single matched-node percentage improvement across power, throughput and area. Do not substitute wirelength for silicon performance.

Next comparable measurement

Publish watts, workload throughput and square millimeters together, with process node, voltage, temperature, timing and area constraints fixed. Preserve this dated observation; append future results with their model/system version, denominator, budget and evidence level rather than overwriting it.

Open the full research note

Useful AI efficiency

40%estimated progress

What we track

Joules and total dollars per training run reaching fixed quality, or per inference meeting fixed accuracy and latency. Include memory and communication overhead.

Why this estimate?

Standardized inference benchmarks support reproducible efficiency assessment across systems. Throughput gains alone do not establish AI-directed gains in full energy and cost efficiency.

Advancements

Google Ironwood TPU: 2x performance per watt over TrilliumApril 9, 2025. Google announced its seventh-generation TPU, Ironwood, stating 2x performance per watt relative to Trillium and nearly 30x the power efficiency of its first Cloud TPU from 2018, with 4,614 TFLOPs peak compute and 192 GB of high-bandwidth memory per chip.
Google measures 0.24 Wh per median Gemini text prompt, down 33x in a yearAugust 21, 2025. Google reported that the median Gemini Apps text prompt uses 0.24 Wh of energy and about 0.26 mL of water, and that over one year energy per median prompt fell 33x and carbon footprint 44x through software efficiency work and clean energy procurement.
MLPerf: accelerator throughput up 5.58× since early 2024September 17, 2026. MLCommons reports median per-accelerator Llama 2 70B Server throughput improving 5.58-fold across six rounds since v4.0 in early 2024.

Read the dated findings and sources

Status: Measured throughput trend; energy/cost attribution incomplete. Sources accessed November 7, 2026. This is a documentary baseline, not an independent replication or an assertion of the worldwide best result. An unknown measurement is not zero.

Dated findings

September 17, 2026: MLCommons reports median per-accelerator Llama 2 70B Server throughput improving 5.58-fold across six rounds since v4.0 in early 2024. MLCommons: MLPerf Inference v6.1.

Interpretation and tracking value

Hardware, software and numerical precision changed. Throughput is not joules or total dollars per fixed-quality result, nor proof of AI-designed hardware gains.

Next comparable measurement

Compare qualified submissions at matched accuracy and latency; include measured system power, memory, networking, utilization and amortized costs. Preserve this dated observation; append future results with their model/system version, denominator, budget and evidence level rather than overwriting it.

Open the full research note